Large memory arrays, such as static read access memory (SRAM) and configurable RAM (CRAM), typically are comprised of a plurality of memory cells that are configurable by biasing selected n-channel metal-oxide-semiconductor (NMOS) or p-channel metal-oxide-semiconductor (PMOS) transistors. NMOS and PMOS integrated circuits have four terminals—a drain, a source, a gate, and a body. Both types of NMOS and PMOS transistors are associated with significant leakage current during an idling state when a bias voltage is not applied across the gate and source.
This leakage current results in increased power usage for devices having large memory arrays, such as programmable logic devices (PLD's), microprocessors, and similar programmable devices. The performance of modern integrated circuits is often limited by power consumption considerations. Circuits with poor power efficiency place undesirable demands on system designers. By way of examples, power supply capacity may need to be increased, thermal management issues may need to be addressed, and circuit designs may need to be altered to accommodate inefficient circuitry.
It would be beneficial to provide improved methods and apparatus for reducing leakage current in memory arrays.